Prof. Dr. Jürgen Teich
Department of Computer Science
Our research centers around the systematic design (CAD) of hardware/software systems, ranging from embedded systems to HPC platforms. One principal research direction is domain-specific computing that tries to tackle the very complex programming and design challenge of parallel heterogeneous computer architectures. Domain-specific computing drastically separates the concerns of algorithm development and target architecture implementation, including parallelization and low-level implementation details. The key idea is to take advantage of the knowledge being inherent in a particular problem area or field of application, i.e., a particular domain, in a well-directed manner and thus, to master the complexity of heterogeneous systems. Such domain knowledge can be captured by reasonable abstractions, augmentations, and notations, e.g., libraries, Domain-specific programming languages (DSLs), or combinations of both (e.g., embedded DSLs implemented via template metaprogramming). On this basis, patterns can be utilized to transform and optimize the input description in a goal-oriented way during compilation, and, finally, to generate code for a specific target architecture. Thus, DSLs provide high productivity plus typically also high performance. We develop DSLs and target platform languages to capture both domain and architecture knowledge, which is utilized during the different phases of compilation, parallelization, mapping, as well as code generation for a wide variety of architectures, e.g., multi-core processors, GPUs, MPSoCs, FPGAs. All these steps usually go along with optimizing and exploring the vast space of design options and trading off multiple objectives, such as performance, cost, energy, or reliability.
Research projects
- Diffusion-weighted imaging and quantitative susceptibility mapping of the breast, liver, prostate, and brain
- Development of new MRI pulse sequences
- Development of new MRI post-processing schemes
- Joint evaluation of new MR methods with radiology
- Domain-specific Computing for Medical imaging
- Hipacc – the Heterogeneous Image Processing Acceleration Framework
- AI Laboratory for System-level Design of ML-based Signal Processing Applications
- Architecture Modeling and Exploration of Algorithms for Medical Image Processing
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SpiNAPSE: Spiking Neural Architectures on Programmable System-on-Chips for Energy Efficiency
(Third Party Funds Single)
Project leader: ,
Term: 1. January 2026 - 31. December 2028
Acronym: SpiNAPSE
Funding source: IndustrieThis project investigates end-to-end workflows to model, train, and deploy spiking neural networks (SNNs) on FPGA-based PSoCs (programmable system-on-a-chip, including, among other components, programmable logic, i.e., an embedded FPGA) for energy-efficient, low-latency edge AI. It thereby tackles key challenges, such as immature approaches for training and data conversion, fragmented toolchains, missing benchmarks, and hardware mapping limitations, by developing a modular SNN software pipeline, designing scalable FPGA accelerators, and prototyping a proof-of-concept demonstrator. The expected outcomes include automated model-to-bitstream flows, the evaluation of speed and energy efficiency against established baselines, and a provision of design guidelines for developing hardware-accelerated SNNs.The ultimate goal of this project, in cooperation with the Schaeffler Hub for Advanced Research at Friedrich-Alexander-Universität Erlangen-Nürnberg (SHARE at FAU), funded by Schaeffler, is to advance the modeling and training of SNNs as well as the respective design of digital hardware accelerators for SNNs to enable fast, accurate, and energy-efficient computation for the next generation of edge-AI applications, while exploring their potential and applicability, particularly across domains such as industrial automation, electric mobility, and robotics.
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NA³Os: Neural Approximate Accelerator Architecture Optimization for DNN Inference on Lightweight FPGAs
(Third Party Funds Single)
Project leader: ,
Term: 1. May 2024 - 30. April 2027
Acronym: NA³Os
Funding source: DFG-Einzelförderung / Sachbeihilfe (EIN-SBH)Embedded Machine Learning (ML) constitutes an admittedly fast-growing field that comprises ML algorithms, hardware, and software capable of performing on-device sensor data analyses at extremely low power, enabling thus several always-on and battery-powered applications and services. Running ML-based applications on embedded edge devices witnesses a phenomenal research and business interest for many reasons, including accessibility, privacy, latency, cost, and security. Embedded ML is primarily represented by artificial intelligence (AI) at the edge (EdgeAI) and on tiny, ultra resource constrained devices, a.k.a. TinyML. TinyML poses requirements for energy efficiency but also low latency as well as to retain accuracy in acceptable levels mandating, thus, optimization of the software and hardware stack.
GPUs form the default platform for DNN training workloads, due to their high parallelism computing originating by the massive number of processing cores. Though, GPU is often not an optimal solution for DNN inference acceleration due to the high energy-cost and the lack of reconfigurability, especially for high sparsity models or customized architectures. On the other hand, Field Programmable Gate Arrays (FPGAs) have a unique privilege of potentially lower latency and higher efficiency than GPUs while offering high customization and faster time-to-market combined with potentially longer useful life than ASIC solutions.
In the context of TinyML, NA³Os focuses on a neural approximate accelerator-architecture co-search targeting specifically lightweight FPGA devices. This project investigates design techniques to optimally and automatically map DNNs to resource- constrained FPGAs while exploiting principles of approximate computing. Our particular topics of investigation include:- Efficient mapping of DNN operations onto approximate hardware components (e.g., multipliers, adders, DSP Blocks, BRAMs).
- Techniques for fast and automated design space exploration of mappings of DNNs defined by a set of approximate operators and a set of FPGA platform constraints.
- Investigation of a hardware-aware neural architecture co-search methodology targeting FPGA-based DNN accelerators.
- Evaluation of robustness vs. energy efficiency tradeoffs.
- Finally, all developed methods shall be evaluated experimentally by providing a proper synthesis path and comparing the quality of generated solutions with state-of-the-art solutions.
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DI-EDAI: Open-Source Design Tools for the Co-Development of AI Algorithms and AI Chips
(Third Party Funds Single)
Project leader: ,
Term: 1. May 2024 - 30. April 2027
Acronym: DI-EDAI
Funding source: Bundesministerium für Forschung, Technologie und Raumfahrt (BMFTR)
URL: https://www.elektronikforschung.de/projekte/di-edaiMotivation
Chip design is the essential step when developing microelectronics for specific products and applications. Competence in chip design can strengthen Germany's innovation and competitiveness and increase its technological sovereignty in Europe. In order to leverage this potential, the German and European chip design ecosystem is to be expanded. To this end, the BMBF has launched the Microelectronics Design Initiative with four key areas of focus: a strong network as a central exchange platform, training and further education for talented individuals and specialists, research projects to strengthen design capabilities, and expanding research structures.
Project Goals
The aim of the project is to develop modern AI chips that are designed with a particular focus on security, trustworthiness, and energy efficiency in various application scenarios. Another goal is to implement a seamless transition from software-based AI algorithm development to efficient hardware implementation. The focus here is on the close linking of AI and hardware in the design process as well as the development of various AI accelerators and corresponding architectures. The end result should be an automated design methodology that extends from the AI software to the AI hardware.
The focus of our chair within DI-EDAI is, in particular, on the development of a co-exploration approach that optimizes both neural network models and associated AI-specific microprocessor extensions, taking into account non-functional requirements (e.g., cost, speed, accuracy, energy, security). The results, in the form of hardware blocks and EDA software, shall be published as open source and contribute to creating an ecosystem for designing sustainable and transparent AI systems.
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HiLoDa Nets: Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology
(Third Party Funds Single)
Project leader:
Term: 1. March 2024 - 1. March 2027
Acronym: HiLoDa Nets
Funding source: Deutsche Forschungsgemeinschaft (DFG)
URL: https://www.cs12.tf.fau.de/forschung/projekte/hiloda-nets/High throughput data and signal processing applications can be specified preferably by dataflow networks, as these naturally allow the exploitation of parallelism as well globally (at the level of a network of communicating actors) as locally at the actor level, e.g., by implementing each actor as a hardware circuit. Today, there exist a few system-level design approaches to aid an algorithm designer in compiling a dataflow network to a set of processors or, alternatively, to synthesize the network directly in hardware for achieving high processing speeds. But embedded systems, particularly in the context of IoT applications, have additional requirements: Safe operation, even in an environment of intermittent power shortages, and in general (ultra-)low power requirements. Altogether, these requirements seem to be contradictory.
Our proposed project named HiLoDa (High performance, (ultra-Low) power Dataflow) Nets attacks this obvious discrepancy and conflict in requirements by a) introducing, exploiting, and integrating for the first time emerging FeFET technology for the design of actor networks, i.e., by investigating and designing persistable FIFO-based memory units. b) In particular, circuit devices being able to operate in mixed volatile/non-volatile mode of operation shall be modeled, characterized, and designed. c) By combining the system-level concept of dataflow, which is based on self-scheduled activations of computations with emerging CMOS-compatible FeFET technology, inactive actors or even subnets shall inherit the capability of self-powering (down and wakeup). In addition, for a continuously safe mode of operation, a down-powering must also be triggered upon any intermittent shortage of power supply. Analogously, actors shall perform an auto-wakeup after recovery from a power shortage but also subject to fireability.
HiLoDa Nets will be able to combine high clock-speed data processing of each synthesized actor circuit in power-on mode and automatic state retention using FeFET technology in power-off mode, self-triggered during time intervals of either data unavailability or power shortage. d) A fully automatic cross-layer synthesis from system-level dataflow specification to optimized circuit implementation involving FeFET devices shall be developed. This includes e) the DSE (design space exploration) of actor clusterings at the system level to explore individual power domains for the optimization of throughput, circuit cost, energy savings, and endurance. Finally, f) HiLoDa Nets shall be compared to conventional CMOS technology implementations with respect to energy consumption for applications such as spiking neural networks. Likewise, shutdown (backup) and recovery latencies from power shortages shall be evaluated and optimized.
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HYPNOS: HYPNOS – Co-Design of Persistent, Energy-efficient and High-speed Embedded Processor Systems with Hybrid Volatility Memory Organisation
(Third Party Funds Group – Sub project)
Overall project: DFG Priority Programme (SPP) 2037 - Disruptive Memory Technologies
Project leader: ,
Term: 21. September 2022 - 21. September 2028
Acronym: HYPNOS
Funding source: DFG / Schwerpunktprogramm (SPP)
URL: https://spp2377.uos.de/This project is funded by the German Research Foundation (DFG) within the Priority Program SPP 2377 "Scalable Data Management for Future Hardware".
HYPNOS explores how emerging non-volatile memory (NVM) technologies could beneficially replace not only main memory in modern embedded processor architectures, but potentially also one or multiple levels of the cache hierarchy or even the registers and how to optimize such a hybrid-volatile memory hierarchy for offering high speed and low energy tradeoffs for a multitude of application programs while providing persistence of data structures and processing state in a simple and efficient way.
On the one hand, completely non-volatile (memory) processors (NVPs) that have emerged for IoT devices are known to suffer from low write times of current NVM technologies as well as by orders of magnitude lower endurance than, e.g., SRAM, thus prohibiting an operation at GHz speeds. On the other hand, existing NVM main memory computer solutions suffer from the need of the programmer to explicitly persist data structures through the cache hierarchy.
HYPNOS (Named after the Greek god of sleep.) systematically attacks this intertwined performance/endurance/programmability gap by taking a hardware/software co-design approach:
Our investigations include techniques for
a) design space exploration of hybrid NVM memory processor architectures} wrt. speed and energy consumption including hybrid (mixed volatile) register and cache-level designs,
b) offering instruction-level persistence for (non-transactional) programs in case of, e.g., instantaneous power failures through low-cost and low-latency control unit (hardware) design of checkpointing and recovery functions, and additionally providing
c) application-programmer (software) persistence control on a multi-core HyPNOS system for user-defined checkpointing and recovery from these and other errors or access conflicts backed by size-limited hardware transactional memory (HTM).
d) The explored processor architecture designs and different types of NVM technologies will be systematically evaluated for achievable speed and energy gains, and for testing co-designed backup and recovery mechanisms, e.g., wakeup latencies, etc., using a gem5-based multi-core simulation platform and using ARM processors with HTM instruction extensions.
As benchmarks, i) simple data structures, ii) sensor (peripheral device) I/O and finally iii) transactional database applications shall be investigated and evaluated.
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GRK 2475: GRK2475: Cyberkriminalität und Forensische Informatik
(Third Party Funds Group – Overall project)
Project leader: ,
Term: 1. October 2019 - 30. September 2028
Acronym: GRK 2475
Funding source: DFG / Graduiertenkolleg (GRK)
URL: https://www.cybercrime.fau.de/Neue Informationstechnologien erlauben immer auch neue Möglichkeiten der Begehung von Straftaten, die häufig mit dem Begriff „Cyberkriminalität“ belegt werden. Im Hinblick auf die Abhängigkeit hochentwickelter Gesellschaften von (kritischen) IT-Infrastrukturen bedroht diese Kriminalität heute die Stabilität unseres Wirtschafts- und Gesellschaftssystems. Die neuen Informationstechnologien eröffnen jedoch auch neue Möglichkeiten der Strafverfolgung, wie etwa automatisierte Datensammlung und –auswertung im Netz oder heimlich in IT-Systeme eingeschleuste Überwachungsprogramme (Trojaner).
Die Effektivität dieser neuen Methoden der so genannten „forensischen Informatik“ provoziert regelmäßig die Frage nach den Auswirkungen auf die Grundrechte der Betroffenen. Die Begrenzung des Rechtsraums auf Nationalstaaten schafft zusätzliche Probleme. In diesem Vorhaben haben sich etablierte Wissenschaftler aus der Informatik und den Rechtswissenschaften zusammengeschlossen, um das noch recht unscharfe Forschungsfeld Cyberkriminalität sowie Strafbarkeit und Strafverfolgung von Cyberkriminalität systematisch zu erschließen, grundlegende Zusammenhänge aufzudecken und das Gebiet insgesamt einer besseren Handhabe zugänglich zu machen.
Die Forschung im Graduiertenkolleg hat darum hier das Potential, die technisch-methodischen Standards des Umgangs mit digitalen Spuren, deren Nutzen für die Strafverfolgung sowie die nationale wie internationale Rechtsinterpretation und -gestaltung auf viele Jahre hinaus zu prägen. Gleichzeitig wirken wir in diesem Bereich dem Mangel an wissenschaftlich-methodisch geschultem Fachpersonal in Wirtschaft, Verwaltung und bei den Strafverfolgungsbehörden entgegen.
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GRK 2475: Cybercrime and Forensic Computing -- Hardware Security
(Third Party Funds Group – Sub project)
Overall project: Research Training Group 2475: Cybercrime and Forensic Computing
Project leader: ,
Term: 1. October 2019 - 1. October 2028
Acronym: GRK 2475
Funding source: DFG / Graduiertenkolleg (GRK)
URL: https://www.cybercrime.fau.deThis project is funded by the German Research Foundation (DFG) within the Research Training Group 2475 "Cybercrime and Forensic Computing".Cybercrime is becoming an ever greater threat in view of the growing societal importance of information technology. At the same time, new opportunities are emerging for law enforcement, such as automated data collection and analysis on the Internet or via surveillance programs. But how do you deal with the fundamental rights of those affected when "forensic informatics" is used? The RTG "Cybercrime and Forensic Informatics" brings together experts in computer science and law to investigate the research field of "prosecution of cybercrime" in a systematic way.At the Chair of Computer Science 12, aspects of hardware security are investigated. The focus is on researching techniques to extract information and traces from technical devices via side channels. The physical implementation of a system emits further, so-called side-channel information to the environment in addition to the actual processing of input data to output data. Known side channels are, for example, the data-dependent time behavior of an algorithm implementation, as well as power consumption, electromagnetic radiation and temperature development.
2026
- Deutel, M., Marchl, A., Plinge, A., Hannig, F., & Teich, J. (2026). EmbeddedAD: Efficient Anomaly Detection on SoCs via Vector-Quantized Reverse Distillation. In Proceedings of the 39th IEEE International System-on-Chip Conference (SOCC). Heidelberg, DE.
- Hahn, T., Wildermann, S., & Teich, J. (2026). FLICS: FPGA-acceLerated Ingestion of documents into Columnar Storage. In Proceedings of the 39th GI/ITG International Conference on Architecture of Computing Systems. Mainz, DE.
- Heidorn, C., Hannig, F., Riedelbauch, D., Strohmeyer, C., & Teich, J. (2026). Entropy Sampling-Based Neural Architecture Search for Resource-Constrained Microcontroller Targets. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE) (pp. 1-7). Verona, IT: IEEE.
- Heidorn, C., Hannig, F., Riedelbauch, D., Strohmeyer, C., & Teich, J. (2026). OpTC - Automatic Compression and Performance Estimation for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. Communications in Computer and Information Science, 2954, 125–145. https://doi.org/10.1007/978-3-032-23187-1_7
- Heidorn, C., Herderich, T., & Teich, J. (2026). Dynamically Adaptable Ensemble Proxies for Training-Free Neural Architecture Search. In Proceedings of the The 6th Workshop on Machine Learning and Systems. Edinburgh, GB: ACM.
- Hernandez Morales, J.J., Mentzos, G., Hannig, F., Balaskas, K., Zervakis, G., Henkel, J., & Teich, J. (2026). Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition. arXiv.
- Karim, A., Darne, B., Matrangolo, P.-A., Falk, J., O'Connor, I., Marchand, C.,... Teich, J. (2026). FeMFET-based High-Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. Microprocessors and Microsystems.
- Mahesh Nirmala, A., Walter, D., Hannig, F., & Teich, J. (2026). Symbolic Energy Analysis for Nested Loop Accelerators. In Proceedings of the 37th IEEE International Conference on Application-specific Systems, Architectures and Processors. Imperial College London London, UK.
- Meißner, S., Wildermann, S., Peter, N., Wilbert, N., & Teich, J. (2026). Hints for Program-Driven Control of Hybrid Volatile/Non-Volatile Caches. In Proceedings of the 4th Workshop on Disruptive Memory Systems. Prag, CZ.
- Sixdenier, P.-L., Deutel, M., Wildermann, S., & Teich, J. (2026). Early-Exit Forecasting of Deep Neural Networks on Energy-Harvesting Edge Devices. In International Workshops of ECML PKDD 2026. Naples, Italy, IT: Springer.
- Sotiropoulos, G., Frombach, F., Höfer, J., Harbaum, T., Becker, J., Thorøe, H.I.,... Sigl, G. (2026). Multi-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAI. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE) (pp. 1-7). Verona, IT: IEEE.
- Walter, D., Halm, M., Seidel, D., Ghosh, I., Heidorn, C., Hannig, F., & Teich, J. (2026). Modeling and Mapping of Regular Nested Loops on Processor Arrays: CGRAs vs. TCPAs. In Proceedings of the 29. Workshop zu Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Würzburg, DE.
- Walter, D., Hannig, F., & Teich, J. (2026). Zero-Overhead Loop Control for Tightly Coupled Processor Arrays (TCPAs). In Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.
- Wittmann, J., Sabih, M., Hannig, F., & Teich, J. (2026). RISC-V Extensions and One-Shot Training for the Acceleration of Mixed-Precision Quantized DNNs. In International Workshops of ECML PKDD 2026. Neapel, IT: Springer.
2025
- Darne, B., Karim, A., Matrangolo, P.-A., Falk, J., O'Connor, I., Marchand, C.,... Teich, J. (2025). FeMFET-based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. In Proceedings of the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (pp. 1-8). Barcelona, Spain, ES.
- Deutel, M., Kontes, G., Mutschler, C., & Teich, J. (2025). Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML. ACM Transactions on Evolutionary Learning and Optimization, 5(3), 1-21. https://doi.org/10.1145/3715012
- Deutel, M., Kontes, G., Mutschler, C., & Teich, J. (2025). Multi-Objective Bayesian Optimization with Reinforcement Learning for Edge Deployment of DNNs on Microcontrollers. In ACM (Eds.), GECCO '25 Companion: Proceedings of the Genetic and Evolutionary Computation Conference Companion (pp. 19-20). Málaga, ES.
- Deutel, M., Mutschler, C., & Teich, J. (2025). microYOLO: Towards Single-Shot Object Detection on Microcontrollers. In University of Turin (Eds.), International Workshops of ECML PKDD 2023, Turin, Italy, September 18–22, 2023, Revised Selected Papers, Part V (pp. 163-169). Torino, IT: Springer, Cham.
- Deutel, M., Plinge, A., Seuss, D., Mutschler, C., Hannig, F., & Teich, J. (2025). Unsupervised Learning of Variational Autoencoders on Cortex-M Microcontrollers. In Proceedings of the IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (pp. 469-476). Singapore, SG: IEEE.
- Esper, K., Wildermann, S., & Teich, J. (2025). Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. In Proceedings of the 30th Asia and South Pacific Design Automation Conference (pp. 1160-1166). Tokyo, JP: ACM.
- Esper, K., Wildermann, S., & Teich, J. (2025). Run-time Requirement Enforcement of Safety Requirements of Human-Robot Interactions. In 2025 11th International Conference on Automation, Robotics, and Applications (ICARA) (pp. 111-115). Zagreb, HR: IEEE.
- Groth, S., Heidorn, C., Schmid, M., Teich, J., & Hannig, F. (2025). Latency-Constrained Neural Architecture Search for U-Nets on Graphics Processing Units. In Proceedings of the 28th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), (pp. 52-60). Rostock, DE: VDE.
- Hahn, T., Hofmann, J., Wildermann, S., & Teich, J. (2025). FSST Compression of JSON Data on FPGAs. In Architecture of Computing Systems: 38th International Conference, ARCS 2025, Kiel, Germany, April 22–24, 2025, Proceedings (pp. 48–62). Kiel, DE: Berlin, Heidelberg: Springer-Verlag.
- Hahn, T., Langohr, M., Becher, A., Beena Gopalakrishnan Nair, L., Meyer-Wegener, K., Teich, J., & Wildermann, S. (2025). ReProVide: Query Optimization and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. In Scalable Data Management for Future Hardware. (pp. 171-197).
- Hahn, T., Langohr, M., Meißner, S., Döring, B., Wildermann, S., Meyer-Wegener, K., & Teich, J. (2025). ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. In Proceedings of the 21st Conference on Database Systems for Business, Technology and Web (pp. 899-906). Bamberg, DE.
- Hernandez Morales, J.J., Hannig, F., & Teich, J. (2025). A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices. In Sven Tomforde, Christian Krupitzer, Stephane Vialle, Estela Suarez, and Thilo Pionteck (Eds.), Architecture of Computing Systems, 38th International Conference, ARCS 2025, Kiel, Germany, April 22–24, 2025, Proceedings (pp. 172--188). Kiel, DE: Springer.
- Karim, A., Falk, J., & Teich, J. (2025). Exploration of Clock and Power Gating Tradeoffs for the Design of Self-Powering Dataflow Networks. In VDE ITG; VDE/VDI GMM; GI (Eds.), Proceedings of the 28th Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (pp. 1-10). Rostock Warnemünde, DE: Berlin - Offenbach: VDE VERLAG.
- Krüger, P., Wildermann, S., & Teich, J. (2025). Breaking Confidentiality of XTS-AES Encrypted Data at Rest on Microprocessors using Electromagnetic Side-Channel Attacks. In IEEE (Eds.), 2025 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (pp. 450-461). San Jose, US.
- Lamberti, P., Esper, K., Spieck, J., Velasco-Guillen, R.J., Beckerle, P., & Teich, J. (2025). Enforcing Safety Requirements of a Knee Orthosis Using Finite State Machines. In 2024 2nd International Conference on Integrated Systems in Medical Technologies (ISMT) (pp. 1-6). Erlangen, DE: IEEE.
- Plagwitz, P., Hannig, F., Teich, J., & Keszocze, O. (2025). DSL-based SNN Accelerator Design using Chisel. Microprocessors and Microsystems, 118. https://doi.org/10.1016/j.micpro.2025.105187
- Sabih, M., Abdo, M., Hannig, F., & Teich, J. (2025). Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks using RISC-V Custom Functional Units. IEEE Embedded Systems Letters, 17(5), 329-332. https://doi.org/10.1109/LES.2025.3600565
- Sabih, M., Abdo, M., Hannig, F., & Teich, J. (2025). Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units. IEEE Embedded Systems Letters, 17(5), 329-332. https://doi.org/10.1109/LES.2025.3600565
- Sesli, B., Sabih, M., Hannig, F., & Teich, J. (2025). Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. In IEEE (Eds.), Proceedings of the International Conference on Computer Aided Design (ICCAD). Munich, DE.
- Seum, T., Krüger, P., Wildermann, S., & Teich, J. (2025). Die Verwendung von Seitenkanalangriffen durch die Strafverfolgungsbehörden Impraktikabel oder ein mächtiges Werkzeug? MultiMedia und Recht, 2/2025, 98-104.
- Sixdenier, P.-L., Deutel, M., & Teich, J. (2025). Early-Exit Neural Architecture Search for Energy-Harvesting Edge Computing. In 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). Singapore, SG: IEEE.
- Sixdenier, P.-L., Wildermann, S., Arockiaraj, J., & Teich, J. (2025). WiP Paper: Utility-Aware Transmission of Sensor Data on Energy-Harvesting IoT Gateways. In 22nd International Conference on Embedded Wireless Systems and Networks (EWSN 2025). Leuven, Belgium, BE.
- Spieck, J., Walter, D., Waschkeit, J., & Teich, J. (2025). Co-Design of Sustainable Embedded Systems-on-Chip. In Design, Automation and Test in Europe Conference. Lyon, FR.
- Spieck, J., Walter, D., Waschkeit, J., & Teich, J. (2025). Co-Design of Systems-on-Chip for Sustainability. In Proceedings of the NG-RES 2025: Sixth Workshop on Next Generation Real-Time Embedded Systems. Barcelona, Spain: Schloss Dagstuhl – Leibniz-Zentrum für Informatik.
- Tahoori, M., Becker, J., Henkel, J., Kunz, W., Schlichtmann, U., Sigl, G.,... Wehn, N. (2025). Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). In 2025 Design, Automation & Test in Europe Conference (DATE). Lyon, FR: Institute of Electrical and Electronics Engineers Inc..
- Tahoori, M., Meyers, V., Sadeghipour Roodsari, M., Xu, H., Becker, J., Harbaum, T.,... Shelkamy Ali, M. (2025). Special Session – Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. In ACM (Eds.), Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (pp. 23-32). Taipei, TW.
- Walter, D., Brand, M., Heidorn, C., Witterauf, M., Hannig, F., & Teich, J. (2025). Europractice activity report 2024.
- Walter, D., Halm, M., Seidel, D., Ghosh, I., Heidorn, C., Hannig, F., & Teich, J. (2025). Evaluation of CGRA Toolchains. In In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC). Lyon, FR.
- Wilbert, N., Szymanski, M., Wildermann, S., Herzog, H., Hoenig, T., & Teich, J. (2025). CHaOS: A Persistent Lightweight Cache Hybridization-aware OS. In Proceedings of the 38th GI/ITG International Conference on Architecture of Computing Systems. Kiel.
- Wildermann, S., Wilbert, N., Häberlein, T., & Teich, J. (2025). Self-powered Embedded Systems: The Role of Non-volatile Memory Technology in IoT Devices. In Gidon Ernst, Matthias Güdemann, Alexander Knapp, Florian Nafz, Frank Ortmeier, Hella Ponsar, Gerhard Schellhorn, Alexander Schiendorfer (Eds.), Go Where the Bugs Are: Essays Dedicated to Wolfgang Reif on the Occasion of His 65th Birthday. (pp. 155-177). Cham: Springer.
2024
- Deutel, M., Hannig, F., Mutschler, C., & Teich, J. (2024). Fused-Layer CNNs for Memory-Efficient Inference on Microcontrollers. In Proceedings of the Workshop on Machine Learning and Compression @ NeurIPS 2024. Vancouver Convention Center, CA.
- Deutel, M., Hannig, F., Mutschler, C., & Teich, J. (2024). On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44(4), 1250 - 1261. https://doi.org/10.1109/TCAD.2024.3484354
- Esper, K., & Teich, J. (2024). History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Patrick Meumeu Yomsi, Stefan Wildermann (Eds.), Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024) (pp. 4:1-4:11). Munich, DE: Saarbrücken/Wadern: Schloss Dagstuhl – Leibniz-Zentrum für Informatik.
- Esper, K., Wildermann, S., & Teich, J. (2024). Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2024 (pp. 1-2). Valencia, ES: IEEE.
- Groth, S., Schmid, M., Teich, J., & Hannig, F. (2024). Estimating the Execution Time of CNN Inference on GPUs. In Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (pp. 53-62). Kaiserslautern, DE.
- Hahn, T., Schüll, D., Wildermann, S., & Teich, J. (2024). ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs. In IEEE Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Kielce.
- Hahn, T., Wildermann, S., & Teich, J. (2024). JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. In IEEE Proceedings of the 34th International Conference on Field-Programmable Logic and Applications. Turin.
- Heidorn, C., Hannig, F., Riedelbauch, D., Strohmeyer, C., & Teich, J. (2024). Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. In SCITEPRESS (Eds.), Proceedings of the 10th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS). Angers, FR.
- Heidorn, C., Hannig, F., Riedelbauch, D., Strohmeyer, C., & Teich, J. (2024). OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers.
- Heidorn, C., Hannig, F., Riedelbauch, D., Strohmeyer, C., & Teich, J. (2024). OpTC – A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. In André Casal Kulzer, Hans-Christian Reuss, Andreas Wagner (Eds.), Proceeding of the 2024 Stuttgart International Symposium on Automotive and Engine Technology (pp. pp 65–81). Stuttgart, DE: Wiesbaden: Springer Vieweg.
- Heidorn, C., Sabih, M., Meyerhöfer, N., Schinabeck, C., Teich, J., & Hannig, F. (2024). Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. International Journal of Parallel Programming, 52, 40 - 58. https://doi.org/10.1007/s10766-024-00760-5
- Karim, A., Falk, J., Schmidt, D., & Teich, J. (2024). Self-Powering Dataflow Networks – Concepts and Implementation. In Proceedings of the 22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) (pp. 69-74). Raleigh, NC, US.
- Krüger, P., Wildermann, S., & Teich, J. (2024). CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. In Association for Computing Machinery (ACM) (Eds.), EUROSEC '24: Proceedings of the 17th European Workshop on System Security (pp. 37-43). Athen, GR.
- Letras, M., Falk, J., & Teich, J. (2024). Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems. IEEE Access, 12, 39748-39769. https://doi.org/10.1109/ACCESS.2024.3375079
- Plagwitz, P., Hannig, F., Teich, J., & Keszöcze, O. (2024). Compiler-based Processor Network Generation for Neural Networks on FPGAs. In Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV) (pp. 41-52). Kaiserslautern, DE.
- Plagwitz, P., Hannig, F., Teich, J., & Keszöcze, O. (2024). DSL-based SNN Accelerator Design using Chisel. In Proceedings of the 27th Euromicro Conference on Digital Systems Design (DSD). Paris, FR: IEEE.
- Plagwitz, P., Hannig, F., Teich, J., & Keszöcze, O. (2024). SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. In Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC). Aveiro, PT: Springer.
- Sabih, M., Karim, A., Wittmann, J., Hannig, F., & Teich, J. (2024). Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. In IEEE (Eds.), Proceedings of International Conference on Field Programmable Technology (FPT) (pp. 1-9). Sydney, Australia, AU.
- Sabih, M., Sesli, B., Hannig, F., & Teich, J. (2024). Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE). Valencia, ES.
- Sixdenier, P.-L., Wildermann, S., & Teich, J. (2024). GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. In Proceedings of the 13th Mediterranean Conference on Embedded Computing (MECO). Budva, Montenegro, ME.
- Spieck, J., Wildermann, S., & Teich, J. (2024). A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Transactions on Design Automation of Electronic Systems. https://doi.org/10.1145/3660633
- Walter, D., Adamtschuk, T., Hannig, F., & Teich, J. (2024). Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. In Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Hong Kong.
- Walter, D., Brand, M., Heidorn, C., Witterauf, M., Hannig, F., & Teich, J. (2024). ALPACA: An Accelerator Chip for Nested Loop Programs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). Singapore, SG.
- Wilbert, N., Wildermann, S., & Teich, J. (2024). Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. In MEMSYS '24: Proceedings of the International Symposium on Memory Systems (pp. 257–269). Washington, D.C., US.
- Wilbert, N., Wildermann, S., & Teich, J. (2024). To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. In Proceedings of the 2nd Workshop on Disruptive Memory Systems (pp. 17 - 24). Austin, TX, US.
2023
- Bosio, A., Barbareschi, M., Savino, A., Han, J., & Teich, J. (2023). Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Design & Test, 40(3), 5-7. https://doi.org/10.1109/MDAT.2022.3221909
- Deutel, M., Woller, P., Mutschler, C., & Teich, J. (2023). Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. In VDE (Eds.), MBMV 2023; 26th Workshop (pp. 12). Freiburg, DE: VDE.
- Esper, K., Spieck, J., Sixdenier, P.-L., Wildermann, S., & Teich, J. (2023). RAVEN: Reinforcement Learning for Generating Verifiable Run-time Requirement Enforcers for MPSoCs. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023) (pp. 7:1 - 7:16). Toulouse, FR: Dagstuhl, Germany: Schloss Dagstuhl -- Leibniz-Zentrum für Informatik.
- Esper, K., Wildermann, S., & Teich, J. (2023). Automatic Synthesis of FSMs for Enforcing Non-Functional Requirements on MPSoCs Using Multi-Objective Evolutionary Algorithms. ACM Transactions on Design Automation of Electronic Systems, 28(6), 1-20. https://doi.org/10.1145/3617832
- Hahn, T., Schüll, D., Wildermann, S., & Teich, J. (2023). An FPGA Avro Parser Generator for Accelerated Data Stream Processing. In Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC). Dresden, DE.
- Hahn, T., Wildermann, S., & Teich, J. (2023). SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs. In IEEE Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications. Göteborg.
- Henkel, J., Sidduh, L., Bauer, L., Teich, J., Wildermann, S., Tahoori, M.B.,... Cheng, H.-Y. (2023). Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES). HAMBURG, DE.
- Letras, M., Falk, J., & Teich, J. (2023). Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks using Multi-Reader Buffers. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Toulouse, FR: Germany.
- Plagwitz, P., Hannig, F., Teich, J., & Keszöcze, O. (2023). To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations.
- Pradhan, C., Letras, M., & Teich, J. (2023). Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. ACM Transactions on Embedded Computing Systems, 22(4), 1-24. https://doi.org/10.1145/3580737
- Sabih, M., Yayla, M., Hannig, F., Teich, J., & Chen, J.-J. (2023). Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. In Eiko Yoneki, Luigi Nardi (Eds.), EuroMLSys '23: Proceedings of the 3rd Workshop on Machine Learning and System (pp. 87–93). Rome, Italy, IT: New York(NY) United States: Association for Computing Machinery (ACM).
- Sixdenier, P.-L., Wildermann, S., Ottens, M., & Teich, J. (2023). Seque: Lean and Energy-aware Data Management for IoT Gateways. In Proceedings of the IEEE International Conference on Edge Computing and Communications (EDGE). Chicago, Illinois USA, US: IEEE.
- Spieck, J., Sixdenier, P.-L., Esper, K., Wildermann, S., & Teich, J. (2023). Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. In 2023 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE) (pp. 23-35). Hamburg, DE.
- Spieck, J., Wildermann, S., & Teich, J. (2023). A Learning-Based Methodology for Scenario-Aware Mapping of Soft Real-Time Applications onto Heterogeneous MPSoCs. ACM Transactions on Design Automation of Electronic Systems, 28(1), 4:1 - 4:40. https://doi.org/10.1145/3529230
- Trautmann, J., Krüger, P., Becher, A., Wildermann, S., & Teich, J. (2023). Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Transactions on Reconfigurable Technology and Systems, 1-27. https://doi.org/10.1145/3635719
2022
- Anantharajaiah, N., Asfour, T., Bader, M., Bauer, L., Becker, J., Bischof, S.,... Zhang, L. (2022). Invasive Computing. FAU University Press.
- Brand, M., Keszöcze, O., & Teich, J. (2022). Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(6), 2661 - 2666. https://doi.org/10.1109/TCSII.2022.3173753
- Brand, P., Hackenberg, B., Falk, J., & Teich, J. (2022). Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. In Proceedings of the International Wireless Communications and Mobile Computing Conference (IWCMC 2022). Dubrovnik.
- Echavarria Gutiérrez, J.A., Keszöcze, O., & Teich, J. (2022). Probability-based DSE of Approximated LUT-based FPGA Designs. In Proceedings of the 15th IEEE Dallas Circuits and Systems Conference. Dallas, US.
- Echavarria Gutiérrez, J.A., Wildermann, S., Keszöcze, O., Khosravi, F., Becher, A., & Teich, J. (2022). Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. it - Information Technology. https://doi.org/10.1515/itit-2021-0040
- Esper, K., Wildermann, S., & Teich, J. (2022). Multi-requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. In Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022) (pp. 2:1--2:13). Budapest, HU: Dagstuhl, Germany: Schloss Dagstuhl -- Leibniz-Zentrum für Informatik.
- Hahn, T., Becher, A., Wildermann, S., & Teich, J. (2022). Raw Filtering of JSON data on FPGAs. In Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe. Antwerpen, BE.
- Hahn, T., Wildermann, S., & Teich, J. (2022). Auto-Tuning of Raw Filters for FPGAs. In IEEE Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications. Belfast, United Kingdom.
- Heidorn, C., Meyerhöfer, N., Schinabeck, C., Hannig, F., & Teich, J. (2022). Hardware-Aware Evolutionary Filter Pruning. In Springer, Cham (Eds.), Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (pp. 283 - 299). Pythagoreio, Samos, GR: Switzerland: Springer Nature.
- Mishra, A., Hannig, F., Teich, J., & Sabih, M. (2022). MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. In IEEE (Eds.), 2022 IEEE 13th International Green and Sustainable Computing Conference (IGSC) (pp. 1-8). Virtual: Pittsburgh, PA, USA: Institute of Electrical and Electronics Engineers (IEEE).
- Plagwitz, P., Hannig, F., & Teich, J. (2022). TRAC: Compilation-based Design of Transformer Accelerators for FPGAs. In IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications. Belfast, United Kingdom.
- Pourmohseni, B., Wildermann, S., Smirnov, F., Meyer, P., & Teich, J. (2022). Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access. https://doi.org/10.1109/ACCESS.2022.3162617
- Sabih, M., Hannig, F., & Teich, J. (2022). DyFiP: Explainable AI-based Dynamic Filter Pruning of Convolutional Neural Networks. In Proceedings of the 2nd European Workshop on Machine Learning and Systems (EuroMLSys) (pp. 109–115). Rennes, France, FR: New York, NY, United States: Association for Computing Machinery (ACM).
- Sixdenier, P.-L., Wildermann, S., Ziegler, D., & Teich, J. (2022). SIDAM: A Design Space Exploration Framework for Multi-Sensor Embedded Systems Powered by Energy Harvesting. In Springer, Cham (Eds.), International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII) (pp. 329-345). Pythagoreio, Samos, GR: Switzerland: Springer Nature.
- Snelting, G., Teich, J., Fried, A., Hannig, F., & Witterauf, M. (2022). Compilation and Code Generation for Invasive Programs. In Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.), Invasive Computing. (pp. 309-333). FAU University Press.
- Sommer, J., Özkan, M.A., Keszöcze, O., & Teich, J. (2022). DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. In IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications. Belfast, United Kingdom, GB.
- Sommer, J., Özkan, M.A., Keszöcze, O., & Teich, J. (2022). Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(11), 3767 - 3778. https://doi.org/10.1109/TCAD.2022.3197512
- Sommer, J., Özkan, M.A., Keszöcze, O., & Teich, J. (2022). Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). Shanghai, CN.
- Spieck, J., Wildermann, S., & Teich, J. (2022). On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. In CODES+ISSS 2022. Shanghai.
- Teich, J., Brand, M., Hannig, F., Heidorn, C., Walter, D., & Witterauf, M. (2022). Invasive Tightly-Coupled Processor Arrays. In Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.), Invasive Computing. (pp. 177-202). FAU University Press.
- Teich, J., Esper, K., Falk, J., Pourmohseni, B., Schwarzer, T., & Wildermann, S. (2022). Basics of Invasive Computing. In Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.), Invasive Computing. (pp. 69-95). FAU University Press.
- Teich, J., Henkel, J., & Herkersdorf, A. (2022). Introduction to Invasive Computing. In Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.), Invasive Computing. (pp. 1-66). FAU University Press.
- Trautmann, J., Beckers, A., Wouters, L., Gierlichs, B., Wildermann, S., Verbauwhede, I., & Teich, J. (2022). Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. In IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) (pp. 345–366). Leuven, Belgium.
- Trautmann, J., Patsiatzis, N., Becher, A., Teich, J., & Wildermann, S. (2022). Real-Time Waveform Matching with a Digitizer at 10 GS/s. In IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications. Belfast, United Kingdom.
- Trautmann, J., Patsiatzis, N., Becher, A., Wildermann, S., & Teich, J. (2022). Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. In Association for Computing Machinery (Eds.), Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. Los Angeles, CA, USA: ACM.
- Trautmann, J., Teich, J., & Wildermann, S. (2022). Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. In 30th IEEE International Symposium on Field-Programmable Custom Computing Machines. New York City, US: IEEE.
2021
- Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F.,... Wende, F. (2021). HighPerMeshes -- A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In Proceedings of the 18th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar) in Euro-Par 2020: Parallel Processing Workshops. Warsaw, PL: Springer.
- Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F.,... Wende, F. (2021). The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids. Concurrency and Computation-Practice & Experience. https://doi.org/10.1002/cpe.6616
- Beena Gopalakrishnan Nair, L., Becher, A., Wildermann, S., Meyer-Wegener, K., & Teich, J. (2021). Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum. https://doi.org/10.1007/s13222-020-00363-7
- Bosio, A., O'Connor, I., Traiola, M., Echavarria Gutiérrez, J.A., Teich, J., Abdullah Hanif, M.,... Bertels, K. (2021). Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. In Proceedings of the 26th IEEE European Test Symposium (ETS). Virtual Conference, BE: IEEE.
- Brand, P., Falk, J., Ah Sue, J., Brendel, J., Hasholzner, R., & Teich, J. (2021). Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Transactions on Mobile Computing, 20(8), 2518-2535. https://doi.org/10.1109/TMC.2020.2988651
- Brand, P., Falk, J., Maier, T., & Teich, J. (2021). Simulating Realistic IoT Network Traffic Using Similarity-based DSE. In 2021 International Conference on Computational Science and Computational Intelligence (CSCI) (pp. 1377-1380). Las Vegas, NV: New York: IEEE.
- Brand, P., Falk, J., Potwigin, E., & Teich, J. (2021). Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. In IEEE (Eds.), Proceedings of the 2021 International Symposium on Networks, Computers and Communications (ISNCC 2021) (pp. 1-6). Canadian University, Citywalk, Dubai, AE: IEEE.
- Echavarria Gutiérrez, J.A., Wildermann, S., Keszöcze, O., Khosravi, F., Becher, A., & Teich, J. (2021). On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. arXiv.org.
- Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2021). Approximate Logic Synthesis of Very Large Boolean Networks. In Design, Automation and Test in Europe, DATE 2021. Alpexpo, Grenoble, FR: IEEE Computer Society.
- Esper, K., Wildermann, S., & Teich, J. (2021). A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems. In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES), OASICS Vol. 87 (pp. 1:1--1:12). Budapest, HU.
- Esper, K., Wildermann, S., & Teich, J. (2021). Enforcement FSMs - Specification and Verification of Non-Functional Properties of Program Executions on MPSoCs. In Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (pp. 21–31). Beijing, CN: New York, NY, USA: Association for Computing Machinery.
- Groth, S., Teich, J., & Hannig, F. (2021). Efficient Application of Tensor Core Units for Convolving Images. In Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems (pp. 1–6). Eindhoven (NL).
- Hannig, F., & Teich, J. (2021). Open Source Hardware. Computer, 54(10), 111-115. https://doi.org/10.1109/MC.2021.3099046
- Heidorn, C., Walter, D., Candir, Y.E., Hannig, F., & Teich, J. (2021). Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. Paper presentation at 31st International Conference on Field Programmable Logic and Applications (FPL), Virtual Conference.
- Keszöcze, O., Brand, M., Witterauf, M., Heidorn, C., & Teich, J. (2021). Aarith: An Arbitrary Precision Number Library. In Proceedings of the ACM/SIGAPP Symposium On Applied Computing. virtual conference, KR.
- Khosravi, F., Raß, A., & Teich, J. (2021). Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Transactions on Evolutionary Learning and Optimization, 1(4), 1-26. https://doi.org/10.1145/3469801
- Letras, M., Falk, J., & Teich, J. (2021). Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. In Proceedings of the 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. München.
- Plagwitz, P., Hannig, F., Ströbel, M., Strohmeyer, C., & Teich, J. (2021). A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. In Proceedings of the 29th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). Virtual Conference: IEEE.
- Qiao, B., Teich, J., & Hannig, F. (2021). An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. In Proceedings of the 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 387-396). Portland, OR, US.
- Sabih, M., Hannig, F., & Teich, J. (2021). Fault-Tolerant Low-Precision DNNs using Explainable AI. In 2021 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). Virtual Workshop: IEEE Xplore.
- Schlumberger, J., Wildermann, S., & Teich, J. (2021). CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. In IEEE (Eds.), 11th IFIP International Conference on New Technologies, Mobility and Security (NTMS) (pp. 1-5). Paris, France, FR.
- Schuster, A., Heidorn, C., Brand, M., Keszöcze, O., & Teich, J. (2021). Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs using Accuracy-Programmable Instruction Set Processors. In Springer, Cham (Eds.), Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021) (pp. 375-389). Virtual Event: Switzerland: Springer Nature.
- Smirnov, F., Pourmohseni, B., Glaß, M., & Teich, J. (2021). Efficient Symbolic Routing Encoding for In-vehicle Network Optimization. In Smart Cities, Green Technologies and Intelligent Transport Systems. (pp. 173 - 199). Springer.
- Spieck, J., Wildermann, S., & Teich, J. (2021). Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. In 3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD). North Carolina State University, Raleigh, NC, USA & Online.
- Streit, F.-J., Krüger, P., Becher, A., Schlumberger, J., Wildermann, S., & Teich, J. (2021). CHOICE – A Tunable PUF-Design for FPGAs. In IEEE Proceedings of the 31th International Conference on Field Programmable Logic and Applications. Dresden, Germany.
- Streit, F.-J., Krüger, P., Becher, A., Wildermann, S., & Teich, J. (2021). Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Transactions on Reconfigurable Technology and Systems, 15(1), 1-27. https://doi.org/10.1145/3491237
- Streit, F.-J., Krüger, P., Becher, A., Wildermann, S., & Teich, J. (2021, December). Design and Evaluation of a Tunable PUF Architecture for FPGAs. Paper presentation at International Conference on Field-Programmable Technology (FPT), Auckland, New Zealand, NZ.
- Streit, F.-J., Wildermann, S., Pschyklenk, M., & Teich, J. (2021). Providing Tamper-Secure SoC Updates through Reconfigurable Hardware. In Springer Proceedings of the 17th International Symposium on Applied Reconfigurable Computing. Rennes, France, FR: Springer Computer Science Proceedings.
- Traiola, M., Echavarria Gutiérrez, J.A., Bosio, A., Teich, J., & O'Connor, I. (2021). Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. In Proceedings of the International Conference on Computer-Aided Design, ICCAD. Virtual conference.
- Walter, D., & Teich, J. (2021). LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays. In Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE). Beijing, China.
- Witterauf, M., Walter, D., Hannig, F., & Teich, J. (2021). Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Transactions on Embedded Computing Systems. https://doi.org/10.1145/3466897
- Özkan, M.A., Ok, B., Qiao, B., Teich, J., & Hannig, F. (2021). HipaccVX: Wedding of OpenVX and DSL-based Code Generation. Journal of Real-Time Image Processing, 18(3), 765 - 777. https://doi.org/10.1007/s11554-020-01015-5
2020
- Aliee, H., Glaß, M., Khosravi, F., & Teich, J. (2020). Uncertainty-Aware Compositional System-Level Reliability Analysis. In Henkel, Jörg, Dutt, Nikil (Eds.), Dependable Embedded Systems..
- Arvind, T.K.R., Brand, M., Heidorn, C., Boppu, S., Hannig, F., & Teich, J. (2020). Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. In Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT). Bhubaneswar, IN: IEEE.
- Beena Gopalakrishnan Nair, L., Becher, A., Meyer-Wegener, K., Wildermann, S., & Teich, J. (2020). SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. In Proceedings of EDBT (pp. 4). Copenhagen, DK.
- Brand, M., Witterauf, M., Bosio, A., & Teich, J. (2020). Anytime Floating-Point Addition and Multiplication – Concepts and Implementations. In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors. Manchester, U.K., GB.
- Brand, P., Sabih, M., Falk, J., Ah Sue, J., & Teich, J. (2020). Clustering-Based Scenario-Aware LTE Grant Prediction. In IEEE (Eds.), Proceedings of the 2020 IEEE Wireless Communications and Networking Conference (WCNC) (pp. 1-7). Seoul: IEEE.
- Echavarria Gutiérrez, J.A., Wildermann, S., Keszöcze, O., & Teich, J. (2020). Probabilistic Error Propagation through Approximated Boolean Networks. In Proceedings of the 57th Annual Design Automation Conference. San Francisco, CA, US.
- Echavarria Gutiérrez, J.A., Wildermann, S., Khosravi, F., & Teich, J. (2020). An Approximate Sequential Multiplier with Segmented Carry Chain and Variable Accuracy. In Proceedings of the AxC20: 5th Workshop on Approximate Computing. San Francisco, CA, US.
- Groth, S., Grünewald, D., Teich, J., & Hannig, F. (2020). A Runtime System for Finite Element Methods in a Partitioned Global Address Space. In Proceedings of the 17th ACM International Conference on Computing Frontiers (CF) (pp. 39-48). Catania, Sicily, Italy, IT: ACM.
- Heidorn, C., Hannig, F., & Teich, J. (2020). Design Space Exploration for Layer-parallel Execution of Convolutional Neural Networks on CGRAs. In Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 26-31). St. Goar, DE: ACM.
- Herkersdorf, A., Engel, M., Glaß, M., Henkel, J., Kleeberger, V.B., Kühn, J.M.,... Weis, C. (2020). RAP Model - Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience. In Henkel, Jörg, Dutt, Nikil (Eds.), Dependable Embedded Systems..
- Keszöcze, O., König, M., Brand, M., & Teich, J. (2020). Error Analysis for Loop Programs using Anytime Instructions in Approximate Computing. In VDE (Eds.), Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Stuttgart, DE: VDE Verlag.
- Lengauer, C., Apel, S., Bolten, M., Chiba, S., Rüde, U., Teich, J.,... Schmitt, J. (2020). ExaStencils: Advanced multigrid solver generation. In Hans-Joachim Bungartz, Severin Reiz, Benjamin Uekermann, Philipp Neumann, Wolfgang E. Nagel (Eds.), Lecture notes in computational science and engineering. (pp. 405-452). Cham: Springer.
- Lengauer, C., Apel, S., Bolten, M., Chiba, S., Rüde, U., Teich, J.,... Schmitt, J. (2020). ExaStencils – Advanced Multigrid Solver Generation. In Hans-Joachim Bungartz, Severin Reiz, Philipp Neumann, Benjamin Uekermann, Wolfgang Nagel (Eds.), Software for Exascale Computing – SPPEXA 2016-2019. (pp. 405-452). Springer.
- Letras, M., Falk, J., Schwarzer, T., & Teich, J. (2020). Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Transactions on Design Automation of Electronic Systems, 26(3), 1–33. https://doi.org/10.1145/3431814
- Mattauch, S., Lohmann, K., Hannig, F., Lohmann, D., & Teich, J. (2020). A Bibliometric Approach for Detecting the Gender Gap in Computer Science. Communications of the ACM, 63(5), 39-45. https://doi.org/10.1145/3376901
- Pourmohseni, B., Glaß, M., Henkel, J., Khdr, H., Rapp, M., Richthammer, V.,... Wildermann, S. (2020). Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective. Journal of Low Power Electronics and Applications, 10(4), 1-37. https://doi.org/10.3390/jlpea10040038
- Pourmohseni, B., Smirnov, F., Wildermann, S., & Teich, J. (2020). Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES) (pp. 5:1-5:14). Bologna, IT.
- Pourmohseni, B., & Teich, J. (2020, March). System-Level Mapping, Analysis, and Management of Real-Time Applications in Many-Core Systems. Poster presentation at PhD Forum at the Design, Automation, and Test in Europe (DATE) Conference and Exhibition, Grenoble, France.
- Qiao, B., Reiche, O., Teich, J., & Hannig, F. (2020). Unveiling Kernel Concurrency in Multiresolution Filters on GPUs with an Image Processing DSL. In Proceedings of the 13th Workshop on General Purpose Processing Using GPU (GPGPU) (pp. 11-20). San Diego, CA, USA, US.
- Qiao, B., Reiche, O., Özkan, M.A., Teich, J., & Hannig, F. (2020). Efficient Parallel Reduction on GPUs with Hipacc. In Proceedings of the 23rd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 58-61). Sankt Goar, DE.
- Qiao, B., Özkan, M.A., Teich, J., & Hannig, F. (2020). The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. In Proceedings of the 57th Annual Design Automation Conference (DAC). San Francisco, CA, US: IEEE.
- Sabih, M., Hannig, F., & Teich, J. (2020). Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks.
- Simon, B., Falk, J., Megow, N., & Teich, J. (2020). Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. In Proceedings of the Workshop on Next Generation Real-Time Embedded Systems (NG-RES) (pp. 2:1-2:13). Bologna, IT.
- Smirnov, F., Pourmohseni, B., & Teich, J. (2020). Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. In PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020) (pp. 957-962). Grenoble, FR: NEW YORK: IEEE.
- Smirnov, F., Pourmohseni, B., & Teich, J. (2020). Using Learning Classifier Systems for the DSE of Dynamically Adaptable Embedded Systems. In Proceedings of the Design, Automation and Test in Europe Conference. Grenoble, FR.
- Spieck, J., Wildermann, S., & Teich, J. (2020). Run-Time Scenario-Based MPSoC Mapping Reconfiguration Using Machine Learning Models. In Post-workshop proceedings of 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD. Canmore, Alberta, Canada, CA.
- Spieck, J., Wildermann, S., & Teich, J. (2020). Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. In Proceedings of the 57th Annual Design Automation Conference (DAC). San Francisco.
- Streit, F.-J., Fritz, F., Becher, A., Wildermann, S., Werner, S., Schmidt-Korth, M.,... Teich, J. (2020). Secure Boot from Non-Volatile Memory for Programmable SoC-Architectures. In IEEE Proceedings of the 13th International Symposium on Hardware Oriented Security and Trust. San José, USA, US.
- Streit, F.-J., Wituschek, S., Pschyklenk, M., Becher, A., Lechner, M., Wildermann, S.,... Teich, J. (2020). Data acquisition and control at the edge: a hardware/software-reconfigurable approach. Production Engineering, 14(3), 365-371. https://doi.org/10.1007/s11740-020-00964-x
- Teich, J., Mahmoody, P., Pourmohseni, B., Roloff, S., Schröder-Preikschat, W., & Wildermann, S. (2020). Run-Time Enforcement of Non-functional Program Properties on MPSoCs. In Jian-Jia Chen (Eds.), A Journey of Embedded and Cyber-Physical Systems. Springer.
- Teich, J., Pourmohseni, B., Keszöcze, O., Spieck, J., & Wildermann, S. (2020). Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 629--636). China National Convention Center, Beijing, China, CN.
- Traiola, M., Echavarria Gutiérrez, J.A., Bosio, A., Teich, J., & O'Connor, I. (2020). Design Space Exploration of an Approximation-Based Fully Reliable TMR Alternative. In Proceedings of the 8th Prague Embedded Systems Workshop. Horoměřice, CZ.
- Walter, D., Witterauf, M., & Teich, J. (2020). Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. In Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE). Jaipur, India.
- Wang, B., Glaß, M., Falk, J., Ahmed, I., & Teich, J. (2020). Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs. In In Proc. of the 33rd International Conference on Architecture of Computing Systems (ARCS). Aachen, DE.
- Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Leißa, R., Hack, S.,... Hannig, F. (2020). AnyHLS: High-Level Synthesis with Partial Evaluation. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). Hamburg, DE.
- Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Leißa, R., Hack, S.,... Hannig, F. (2020). AnyHLS: High-Level Synthesis with Partial Evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3202-3214. https://doi.org/10.1109/TCAD.2020.3012172